Circuit device and method of forming a circuit device having a reduced peak current density

ABSTRACT

In a particular embodiment, a method of forming a field effect transistor (FET) device having a reduced peak current density is disclosed. The method includes forming a field effect transistor (FET) device on a substrate. The FET device includes a drain terminal, a source terminal, a gate terminal, and a body terminal. The method further includes depositing a plurality of metal contacts along a width of a gate terminal of the FET device and forming a wire trace to contact each of the plurality of metal contacts to reduce a gate resistance along the width of the gate terminal.

FIELD OF THE DISCLOSURE

The present disclosure is generally related to a circuit device andmethod of reducing peak current density.

BACKGROUND

In general, power switches may be used to provide a switched powersupply to an inductive load. Inductive loads typically resist a changein current, such that when the power switch is deactivated, theinductive load may operate as a current source to drive current to theswitch. If the power switch is a metal oxide semiconductor field effecttransistor (MOSFET) device that is driving an inductive load, the MOSFETdevice may be controlled by a driver circuit coupled to a gate terminalof the MOSFET device. In a particular example, the driver circuitapplies a gate voltage of approximately zero volts to a gate contactthat is coupled to the gate terminal. However, the inductive load maycontinue to drive current onto a drain terminal of the MOSFET device.

Generally, during a MOSFET on-state to off-state transition, adisplacement current is discharged from the drain terminal of the MOSFETdevice via a drain-to-gate capacitance and through the driver circuitry.However, a gate resistance of the gate terminal increases with adistance from the driver circuitry. Thus, at a remote end of gateterminal, a gate resistance is greater than at an end closest to thedriver circuitry. Assuming a uniform drain-to-gate capacitance, thisnon-uniform gate resistance will lead to a non-uniform localized gatevoltage. Gate terminal regions with higher resistance will sustain ahigher voltage potential, forming increased localized charge in theactive channel of a MOSFET device. Thus, the non-uniform gate resistancecan result in a non-uniform channel current during a switching operationfrom an on-state to an off-state. In a particular embodiment, thenon-uniform channel current can include localized current crowding. Inthis example, the current from the inductive load may continue to flowthrough the active portion of the MOSFET device during the on tooff-state transition, with localized channel regions handling anincreased current density.

In a particular embodiment, a gate contact may be provided at a firstend of the gate terminal and the peak channel current density of theMOSFET device may be shifted toward a second end of the gate terminal.In another particular embodiment, two gate contacts may be provided atopposing ends of the gate terminal, and the peak channel current densityof the MOSFET device is shifted away from the gate contacts toward acenter of the gate terminal. In general, the current at the drain of theMOSFET device is unevenly distributed across a width of the drain,resulting in a peak channel current density at a small portion of theMOSFET device, which may cause overheating and snap-back effects andwhich may damage the MOSFET device.

SUMMARY

In a particular embodiment, a method of forming a field effecttransistor (FET) device having a reduced peak current density isdisclosed. The method includes forming a field effect transistor (FET)device on a substrate. The FET device includes a drain terminal, asource terminal, a body terminal, and a gate terminal. The methodfurther includes depositing a plurality of metal contacts along a widthof a gate terminal of the FET device and forming a wire trace to contacteach of the plurality of metal contacts to reduce a gate resistancealong the width of the gate terminal.

In another particular embodiment, a circuit device includes a substrateand a field effect transistor (FET) device deposited on the substrate.The substrate includes an oxide layer having a plurality of thick oxideregions and a plurality of thin oxide regions. The FET device includes adrain terminal, a source terminal, a body terminal, and a gate terminal.The gate terminal includes a first portion that extends over a thickoxide region of the plurality of thick oxide regions and includes asecond portion that extends over a thin oxide region of the plurality ofthin oxide regions. The circuit device further includes a firstplurality of drain contacts coupled to the drain terminal, a secondplurality of source contacts coupled to the source terminal, a thirdplurality of source contacts coupled to the body terminal, and a fourthplurality of gate contacts coupled to the gate terminal along the firstportion of the gate terminal.

In yet another embodiment, a circuit device includes a switching drivercircuit, an inductive load, and a field effect transistor (FET) device.The FET device includes a drain terminal coupled to the inductive load.The FET device also includes a gate terminal coupled to the switchingdriver circuit and includes a source terminal. The gate terminalincludes a plurality of contacts distributed along a width of the gateterminal to reduce a gate resistance across the width of the gateterminal. The plurality of contacts are adapted to reduce a peak currentdensity of the FET device by distributing current across the width ofthe FET device when the switching driver circuit switches the FET deviceto an off state.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a diagram of a distributed metal oxide semiconductor fieldeffect transistor (MOSFET) device including a gate contact that extendsalong a width of the gate;

FIG. 2 is a top view of a circuit substrate including a representativehigh voltage MOSFET device having a gate contact extending along a widthof the gate;

FIG. 3 is cross-sectional view of the circuit substrate of FIG. 2 takenalong line 3-3 in FIG. 2;

FIG. 4 is a cross-sectional view of the circuit substrate of FIG. 2taken along line 4-4 in FIG. 2;

FIG. 5 is a diagram of a Power over Ethernet (PoE) system that includesa MOSFET device, such as the MOSFET devices illustrated in FIGS. 1-4;

FIG. 6 is a graph illustrating gate voltages at four locations along agate terminal of a conventional metal oxide semiconductor field effecttransistor (MOSFET) device that is driving an inductive load after theconventional MOSFET device is switched off;

FIG. 7 is a graph illustrating gate voltages at four locations along agate terminal of a MOSFET device, such as the MOSFET devices illustratedin FIGS. 1-4, that is driving an inductive load after the MOSFET deviceis switched off;

FIG. 8 is a graph illustrating drain currents at the four locationsalong the gate terminal of the conventional MOSFET device of FIG. 5during an on-state to off-state switching transition;

FIG. 9 is a graph illustrating drain currents at the four locationsalong the gate terminal of the MOSFET device of FIG. 4 after the MOSFETdevice is switched off; and

FIG. 10 is a flow diagram of a particular embodiment of a method offorming a semiconductor device having a reduced peak current density.

DETAILED DESCRIPTION OF THE DRAWINGS

FIG. 1 is a diagram of a circuit device 100 including a metal oxidesemiconductor field effect transistor (MOSFET) device 102. The MOSFETdevice 102 includes a drain terminal 104, a gate terminal 106, and asource terminal 108. The drain terminal 104 is coupled to an inductiveload 120 that operates like a current source. The gate terminal 106 iscoupled to a driver circuit 121, which is adapted to apply a controlsignal to the gate terminal 106 to control the MOSFET device 102.

In general, the MOSFET device 102 has a device width that can be modeledas a series of MOSFET devices 110 arranged in parallel. The series ofMOSFET devices 110 include a first MOSFET device 112, a second MOSFETdevice 114, a third MOSFET device 116, and a fourth MOSFET device 118.In a particular embodiment, the series of MOSFET devices 110 representslices of the MOSFET device 102 at various locations along a width ofthe MOSFET device 102. It should be understood that the series of MOSFETdevices 110 may be represented by any number of MOSFET devices arrangedin parallel.

The first MOSFET device 112 includes a first drain-to-gate capacitance132 and a first gate resistance 122. The second MOSFET device 114includes a second drain-to-gate capacitance 134 and a second gateresistance 124. The third MOSFET device 116 includes a thirddrain-to-gate capacitance 136 and a third gate resistance 126. Thefourth MOSFET device 118 includes a fourth drain-to-gate capacitance 138and a fourth resistance 128. In a particular example, a drain current(I_(D)) flows from the drain terminal 104 through the series oftransistors 110 to the source terminal 108. The drain current (I_(D)) isdistributed such that the first MOSFET device 112 carries a first draincurrent (I_(D1)), the second MOSFET device 114 carries a second draincurrent (I_(D2)), the third MOSFET device 116 carries a third draincurrent (I_(D3)), and a fourth MOSFET device 118 carries a fourth draincurrent (I_(D4)). In a particular embodiment, a sum of the first,second, third, and fourth drain currents (I_(D1), I_(D2), I_(D3), andI_(D4), respectively) is equal to the drain current (I_(D)).

Conventionally, switching a conventional MOSET device from an on-stateto an off state caused the drain current (I_(D)) to be distributedunevenly. In particular, the effective gate resistance increased along awidth of the gate terminal. Accordingly, during a switch from an onstate to an off state, the conventional MOSFET device can operate like acurrent divider circuit. In a particular embodiment, a portion of theMOSFET device is deactivated while other portions remain at leastpartially active. The turn off signal causes one portion of the MOSFETdevice to turn off more quickly than the other portion and the currentis crowded to the other portion. In some instances, the drain current atthe portion of the conventional MOSFET device that is furthest away fromthe gate contact can increase to a level that causes damage to theconventional MOSFET device 102.

Returning to FIG. 1, the MOSFET device 102 includes first, second,third, and fourth gate contacts 142, 144, 146, and 148 that operate tobypass the first, second, third, and fourth gate resistors 122, 124,126, and 128. In a particular embodiment, each of the first, second,third, and fourth gate contacts 142, 144, 146, and 148 have a respectivemetal resistance that is placed in parallel with the first, second,third, and fourth gate resistances 122, 124, 126, and 128, reducing theeffective gate resistance by an order of magnitude. In anotherparticular embodiment, the first, second, third, and fourth gatecontacts 142, 144, 146, and 148 operate to short circuit the gates ofthe first, second, third, and fourth MOSFET devices 112, 114, 116, and118 to the gate contact 106. The first, second, third, and fourth gatecontacts 142, 144, 146, and 148 reduce the effective gate resistances ofeach of the first, second, third, and fourth MOSFET devices 112, 114,116, and 118, allowing the drain current (I_(D)) to be distributedsubstantially evenly across the width of the gate terminal 106, suchthat the first current (ID1), the second current (ID2), the thirdcurrent (ID3), and the fourth current (ID4) are substantially equal.

In a particular embodiment, by shorting/reducing the first, second,third, and fourth gate resistances 122, 124, 126, and 128 using thefirst, second, third, and fourth gate contacts 142, 144, 146, and 148, apeak current density of the circuit device 100 is reduced. Additionally,since the peak current density is reduced, the circuit device 100 may beoperated at a higher operating voltage without destroying the MOSFETdevice 102 when it is switched from an on-state to an off-state.

FIG. 2 is a top view of a circuit device 200 that includes a circuitsubstrate 201 having a relatively high voltage metal oxide semiconductorfield effect transistor (MOSFET) device 202. The MOSFET device 202includes a drain portion 204, a gate portion 206, a source portion 208,and a body portion 209. The drain portion 204, the gate portion 206, thesource portion 208, and the body portion 209 represent heavily dopedportions of the circuit substrate 201. The MOSFET device 202 furtherincludes a drain terminal 214, a gate terminal 216, and a source/bodyterminal 218. The drain, gate, and source/body terminals 214, 216, and218 extend across substantially an entire width (W) of the MOSFET device202. The MOSFET device 202 also includes a plurality of drain contacts224 that are distributed across the drain terminal 214 alongsubstantially the entire width (W) of the MOSFET device 202. The MOSFETdevice 202 further includes a plurality of gate contacts 226 that aredistributed across the gate terminal 216 along substantially the entirewidth (W) of the MOSFET device 202. Further, the MOSFET device 202includes a plurality of source contacts 228 that are distributed acrossthe source/body terminal 218 along substantially the entire width (W) ofthe MOSFET device 202. Further, the MOSFET device 202 includes aplurality of body contacts 229 that are distributed across thesource/body terminal 218 along substantially the entire width (W) of theMOSFET device 202.

In a particular embodiment, the drain terminal 214, the gate terminal216, and the source/body terminal 218 correspond to the drain terminal104, the gate terminal 106, and the source terminal 108 illustrated inFIG. 1. The plurality of gate contacts 226 represent gate contacts suchas the first, second, third, and fourth gate contacts 142, 144, 146, and148 illustrated in FIG. 1.

In a particular embodiment, the gate terminal 216 is deposited over asilicon oxide layer of the circuit substrate 201. The silicon oxidelayer of the circuit substrate 201 has a variable thickness includingthin oxide portions and thick oxide portions. The circuit substrate 201includes a first thin oxide portion 234 of the silicon oxide layer thatis associated with the drain portion 204 of the MOSFET device 202. Thecircuit substrate 201 further includes a second thin oxide portion 236that is associated with the gate and source portions 206 and 208 of theMOSFET device 202. Additionally, the circuit substrate 201 includes athird thin oxide portion 239 that is associated with the body portion209 of the MOSFET device 202. The gate terminal 216 extends over thesecond thin oxide portion 236 and over a relatively thick portion of thesilicon oxide layer. In a particular embodiment, the plurality of gatecontacts 226 is deposited over the thick portion of the silicon oxidelayer. While the plurality of gate contacts 226 are illustrated asdiscrete gate contacts, it should be understood that the plurality ofgate contacts may be a continuous contact that extends across the gateterminal 216 along an entire width (W) of the MOSFET device 202.

FIG. 3 is cross-sectional view 300 of the circuit substrate 201 of FIG.2 taken along line 3-3 in FIG. 2. The circuit substrate 301 includes ap-bulk layer 350, an n-type well 352, a first oxide layer 354, apolycrystalline silicon or polysilicon layer that serves as the gateterminal 216, and a second oxide layer 356. A plurality of gate contacts226 extend from a top surface 380 through the second oxide layer 356 tothe polysilicon layer (gate terminal 216). In general, each of theplurality of gate contacts 226 is deposited over a relatively thickregion of the oxide layer 354. The polysilicon layer (gate terminal 216)extends over a relatively thin portion of the oxide layer 354, which isadjacent to a current channel of the MOSFET device 202.

FIG. 4 is a cross-sectional view 400 of the circuit substrate 201 ofFIG. 2 taken along line 4-4 in FIG. 2. The circuit substrate 200includes a p-bulk material layer 350, an n-well region 352, a firstoxide layer 354, and a second oxide layer 356. The circuit substrate 201includes a MOSFET device 202 having a drain terminal 214, a gateterminal 216, a source/body terminal 218, and a gate-shorting electrode417. The gate terminal 216 may be formed from a polycrystalline siliconor polysilicon material. The drain terminal 214, source/body terminal218, and gate shorting electrode 417 may be formed from a metal such asan aluminum or copper alloy. The first oxide layer 354 includes thefirst thin oxide region 234 adjacent to a heavily doped (N+) region 404within the n-well region 352. The first oxide layer 354 further includesa second thin oxide region 236 adjacent to a heavily doped (N+) region408. The first oxide layer 354 further includes a third thin oxideregion 239 adjacent to a heavily doped (P+) region 409. The polysilicongate terminal 216 is deposited on the first oxide layer 354 and extendspartially over a thick portion and partially over the second thin oxideregion 236. The circuit substrate 201 further includes a drain contact224 that extends from the drain terminal 214 to the N+ region 404. Thecircuit substrate 201 also includes a source contact 228 that extendsfrom the source/body terminal 218 to the N+ region 408. The circuitsubstrate 201 also includes a body contact 229 that extends from thesource/body terminal 218 to the P+ region 409. Further, the circuitsubstrate 201 includes a gate contact 226 that extends from thegate-shorting electrode 417 to the gate terminal 216. The gate terminal216 includes a first gate portion 410 that is deposited over a thickoxide portion 412 of the oxide layer 354 and includes a second gateportion 414 that extends over at least a portion of the second thinoxide region 236. The second gate portion 414 defines a channel length(L) that is a length of an induced current channel allowing current flowbetween the drain and the source terminals 218 and 214, respectively.The gate contact 226 is deposited on the first gate portion 410. In aparticular embodiment, the MOSFET device 202 is a high voltage MOSFETdevice.

In general, the gate contact 226 can be deposited at the first gateportion 410 extending over the thick oxide portion 412 of the firstoxide layer 354 because a photo-etch process that may be used to open avia from the top surface 380 to the gate terminal 216 does not penetratethrough the thick oxide portion 412 to damage the underlying structure.In contrast, if the photo-etch process were performed to etch a via fromthe top surface 380 to the gate terminal over the second thin oxideregion 236, the second thin oxide region 236 may be damaged, resultingin an electrical short circuit between the gate terminal 216 and thesubstrate 201. Further, other structural or physical damage may alsoresult.

FIG. 5 is a block diagram of an embodiment of a Power over Ethernet(PoE) system 500. The PoE system 500 includes a power sourcing equipment(PSE) device 502 that is coupled to a powered device 504 via an Ethernetcable 512. In a PoE system, the Ethernet cable 512 is used to transportboth power and data from the PSE device 502 to the powered device 504.In a particular embodiment, the Ethernet cable 512 includes multiplewire pairs and may carry power via a first wire pair or a second wirepair of the multiple wire pairs. In a particular embodiment, the powereddevice 504 includes one or more diode bridges to rectify a power supplyfrom either the first or second wire pair.

The PSE 502 includes a transformer 514 that is coupled to wires 518 and520 and to the Ethernet cable 512. The wires 518 and 520 are selectivelycoupled to a power source 516 via a power switch 517. The switch 517 maybe a field effect transistor (FET) device, such as the MOSFET devicesillustrated in FIGS. 1-4.

The powered device 504 includes an interface 525, such as an Ethernetconnector (i.e., an RJ-45 Ethernet connector), that couples the Ethernetcable 512 to a transformer 522. The transformer 522 is coupled to thediode bridge 506 via first and second input terminals 524 and 526. Thediode bridge 506 receives a signal via the first and second inputterminals 524 and 526 and rectifies the signal to provide a positivepower supply (Vpos) to a first terminal 528 and to provide a negativepower supply (Vneg) to a second terminal 530. The powered device 504also includes Power over Ethernet (PoE) controller, hot swap, andswitching regulator circuitry 532 that is coupled to the first andsecond terminals 528 and 530 to receive a power supply and to provide aregulated power supply to a first supply terminal 534 and to a secondsupply terminal 536, which are coupled to an output load 538. In aparticular embodiment, the PoE controller, hot swap, and switchingregulator circuitry 532 includes a field effect transistor (FET) device,such as the MOSFET devices illustrated in FIGS. 1-4. In a particularembodiment, the output load 538 may include one or more circuits.

In a particular embodiment, the PoE controller, hot swap, and switchingregulator circuitry 532 includes a logic circuit that is adapted toswitch the controller, hot swap, and switching regulator circuitry 532to an off state. The controller, hot swap, and switching regulatorcircuitry 532 includes a metal oxide semiconductor field effecttransistor (MOSFET) device having a gate terminal coupled to a wiretrace via a plurality of contacts that are deposited along a width ofthe gate terminal. In a particular embodiment, the plurality of contactsare disposed along substantially an entire width of the gate terminal,reducing a peak current density by reducing/shorting a gate resistanceassociated with the MOSFET device to distribute a discharge currentacross the entire width of the MOSFET device when the MOSFET deviceswitches from an on state to an off state.

FIG. 6 is a graph 600 illustrating gate voltages at four locations alonga gate terminal of a conventional metal oxide semiconductor field effecttransistor (MOSFET) device that is driving an inductive load after theconventional MOSFET device is switched off. The graph 600 includes afirst gate voltage 602 that is associated with a first portion of a gateterminal of a conventional MOSFET device that is closest to a drivercircuit (i.e., that is closest to a gate contact). The first gatevoltage 602 decreases from a first level 622 to a second level 624rapidly. The graph 600 further includes a second gate voltage 604 thatdecreases exponentially from the first level 622 to the second level624. The graph 600 also includes a third gate voltage 606 that decreasesfrom the first level 622 and a fourth gate 608 that decreases onlyslightly from the first level 622. In a particular embodiment, since thegate voltages 606 and 608 do not discharge, the gate terminal of theconventional MOSFET device holds a portion of the MOSFET device in anactive state (i.e., an on or conducting state). Thus, the conventionalMOSFET device may continue to conduct current even when the conventionalMOSFET device is switched off.

FIG. 7 is a graph 700 illustrating gate voltages at four locations alonga gate terminal of a MOSFET device, such as the MOSFET devicesillustrated in FIGS. 1-4, that is driving an inductive load after theMOSFET device is switched off. The graph 700 includes a first gatevoltage 702 that is associated with a first portion of a gate terminalof the MOSFET device. The graph 700 also includes a second gate voltage704 that is associated with a second portion of the gate terminal. Thegraph 700 further includes a third gate voltage 706 that is associatedwith a third portion of the gate terminal. The graph 700 also includes afourth gate voltage 708 that is associated with a fourth portion of thegate terminal. In a particular embodiment, the first, second, third, andfourth gate voltages 702, 704, 706 and 708 are substantially equal andthe voltage levels decrease substantially linearly from a first voltagelevel 722 to a second voltage level 724.

In a particular embodiment, the plurality of gate contacts distributedacross a width of the gate terminal of the MOSFET device, as describedwith respect to FIGS. 1-4, allow for distribution of voltage and currentacross the gate terminal when the MOSFET device is switched off. In aparticular embodiment, the distribution of gate contacts reduces aneffective gate resistance across a width of a gate terminal of theMOSFET device, allowing current to be divided substantially evenlyacross a width of the MOSFET device. In a particular example, thedistribution of gate contacts reduces a peak current density in theMOSFET device by equalizing the gate voltage and distributing thecurrent across the width of the MOSFET device. In a particularembodiment, reducing the peak current density across the MOSFET devicemay prevent undesired damage to the MOSFET device and may extend theoperating life of the MOSFET device.

FIG. 8 is a graph 800 illustrating drain currents at the four locationsalong a width of the conventional MOSFET device of FIG. 6 during anon-state to off-state switching transition. The graph 800 includes afirst drain current (I_(D1)) 812 associated with a first portion of theconventional MOSFET device that is closest to a driver circuit. Thegraph 800 also includes a second drain current (I_(D2)) 814, a thirddrain current (I_(D3)) 816, and a fourth drain current (I_(D4)) 818.When the MOSFET device is in an on-state, the first, second, third, andfourth drain currents 812, 814, 816, and 818 are equal to one quarter ofthe overall drain current (i.e., I_(D)/4). When the MOSFET devicetransitions from the on-state to an off-state, the first drain current(I_(D1)) 812 turns off relatively quickly. However, since the inductiveload continues to drive current into the drain of the MOSFET device, thedrain current is distributed along the width of the MOSFET device awayfrom the driver circuit. Thus, the second drain current (I_(D2)) 814initially rises and then turns off. The drain current (I_(D)) is crowdedtoward the third and fourth locations, such that the third drain current(I_(D3)) 816 and the fourth drain current (I_(D4)) 818 increase. Thefourth drain current (I_(D4)) 818 continues to increase as the thirddrain current (I_(D3)) 816 turns off. Finally, the fourth drain current(I_(D4)) 818 turns off. The graph 800 illustrates that the drain currentis crowded toward a current channel of the MOSFET device that isfurthest away from the gate contact.

In a particular embodiment, the drain current is shifted or crowded awayfrom the driver circuit (i.e., away from the gate contact) along thegate terminal until a large portion of the drain current flows through acurrent channel associated with a relatively small portion of theconventional MOSFET device. While the conventional MOSFET device isswitched off, the conventional MOSFET device may continue to conductcurrent. In this condition, the high current through a small area of theconventional MOSFET device can damage the device. Further, as the drainvoltage rises and the drain current increases at a portion of theconventional MOSFET device, the current flow through the current channelcan increase, which may destroy at least a portion of the conventionalMOSFET device. In a particular embodiment, the current may increase dueto impact ionization, snapback effects, other electrical phenomena, orany combination thereof. In a particular embodiment, the term impactionization refers to an electrical phenomenon in which the increasingdrain current coupled with the drain voltage induces creation ofadditional charge carriers, which can create current that flows into theoxide layer and which can be trapped in the oxide layer, adverselyimpacting the transistor operation. In a particular instance, the impactionization can result in an avalanche breakdown that results in anundesired current gain at the current channel. In a particular instance,the impact ionization can result in an increase in body or substratecurrent which may contribute to the turn-on of the parasitic bipolarjunction transistor (BJT) formed by the MOSFET source, body and drainregions. This BJT turn-on may lead to snapback, where the MOSFET drainvoltage collapses while the drain terminal current increases.

FIG. 9 is a graph 800 illustrating drain currents at the four locationsalong the gate terminal of the MOSFET device of FIG. 6 during atransition from an on-state to an off-state. The graph 900 includesfirst, second, third, and fourth drain currents, generally designated at912, 914, 916, and 918, respectively. When the MOSFET device is in anon-state, the first, second, third, and fourth drain currents 912, 914,916, and 918 are approximately equal to one quarter of the drain current(i.e., I_(D)/4), generally indicated at 922. When the MOSFET devicetransitions from an on-state to an off-state, the current level of thefirst drain current 912 transitions quickly, and each of the second,third, and fourth drain currents 914, 916, and 918 also transition fromthe first level 922 to a second level 924 with reduced peak currentdensity. Since the drain current at the four locations along the gateterminal of the MOSFET device have a substantially equal current, thetransistor does not experience current crowding within the currentchannel, and the overall peak current density is reduced. Further, apeak charge density of the MOSFET device is decreased, which allows theMOSFET device to operate at a higher operating voltage.

FIG. 10 is a flow diagram of a particular embodiment of a method offorming a semiconductor device having a reduced peak current density. At1002, a field effect transistor (FET) device is formed on a substrate,where the FET device includes a drain terminal, a source terminal, and agate terminal. Advancing to 1004, a plurality of metal contacts isdeposited along substantially an entire width of a gate terminal of theFET device. In a particular embodiment, the plurality of metal contactsis a metal strip along a width of the gate terminal. Continuing to 1006,a wire trace is formed to contact each of the plurality of metalcontacts to reduce a gate resistance along the entire width of the gateterminal. In a particular embodiment, the wire trace includes a metalresistance in parallel with a gate resistance of the gate terminal. Inanother particular embodiment, the wire trace substantially shorts agate resistance of the gate terminal along the entire width of the gateterminal. The method terminates at 1008.

In a particular embodiment, the gate terminal includes a polysilicondeposit that has a first portion that extends over a thick oxide layerand has a second portion that extends over a relatively thin oxidelayer. The metal contacts are deposited along the width of thepolysilicon deposit over the first portion.

Although the present specification describes components and functionsthat may be implemented in particular embodiments with reference toparticular standards and protocols, the disclosed embodiments are notlimited to such standards and protocols. For example, standards forPower over Ethernet and other power and data transmission techniques(such as broadband Internet over power lines) represent examples of thestate of the art. Such standards are periodically superseded by updatedequivalents having essentially the same functions. For example, the PoEstandard may be superseded by a PoE plus standard that, among othermodifications, allows for transmission of higher voltages to powereddevices that support such voltages. Accordingly, replacement standardsand protocols having the same or similar functions as those disclosedherein are considered equivalents thereof.

The illustrations of the embodiments described herein are intended toprovide a general understanding of the structure of the variousembodiments. The illustrations are not intended to serve as a completedescription of all of the elements and features of apparatus and systemsthat utilize the structures or methods described herein. Many otherembodiments may be apparent to those of skill in the art upon reviewingthe disclosure. Other embodiments may be utilized and derived from thedisclosure, such that structural and logical substitutions and changesmay be made without departing from the scope of the disclosure.Additionally, the illustrations are merely representational and may notbe drawn to scale. Certain proportions within the illustrations may beexaggerated, while other proportions may be reduced. Accordingly, thedisclosure and the figures are to be regarded as illustrative ratherthan restrictive.

The above-disclosed subject matter is to be considered illustrative, andnot restrictive, and the appended claims are intended to cover all suchmodifications, enhancements, and other embodiments, which fall withinthe true spirit and scope of the present invention. Thus, to the maximumextent allowed by law, the scope of the present invention is to bedetermined by the broadest permissible interpretation of the followingclaims and their equivalents, and shall not be restricted or limited bythe foregoing detailed description.

1. A circuit device comprising: a switching driver circuit; an inductiveload; and a field effect transistor (FET) device including a drainterminal coupled to the inductive load and including a gate terminalcoupled to the switching driver circuit, the FET device furtherincluding a source terminal and a body terminal, the gate terminalincluding a plurality of contacts distributed along a width of the gateterminal to reduce a gate resistance across the width of the gateterminal; wherein the plurality of contacts are adapted to reduce a peakcurrent density of the FET device by distributing current across thewidth of the FET device when the switching driver circuit switches theFET device to an off state.
 2. The circuit device of claim 1, whereinthe FET device comprises a switching regulator of a power sourcingequipment device associated with a Power over Ethernet network.
 3. Thecircuit device of claim 1, wherein the FET device comprises a switchingregulator circuit of a powered device that is adapted to communicatewith a Power over Ethernet network.
 4. The circuit device of claim 1,wherein the circuit device comprises a circuit substrate that includesthe FET device, the circuit substrate including a plurality of heavilydoped regions and an oxide layer having a varying thickness that extendsover the plurality of heavily doped regions, the oxide layer including aplurality of thick oxide regions and a plurality of thin oxide regions.5. The circuit device of claim 4, wherein the gate terminal includes afirst portion extending over a thick oxide region along a width of theFET device and a second portion extending over a thin oxide region alongthe width of the FET device.
 6. The circuit device of claim 5, whereinthe plurality of gate contacts are deposited on the first portion of thegate terminal across a width of the FET device.
 7. The circuit device ofclaim 6, further comprising a wire trace coupled to the plurality ofgate contacts to reduce a gate resistance across the width of the FETdevice.
 8. A circuit device comprising: a substrate; a field effecttransistor deposited on the substrate, the field effect transistorincluding a first current electrode, a control electrode, and a secondcurrent electrode, the first current electrode adapted to couple to aninductive load, the first current electrode, the control electrode, andthe second current electrode extending substantially a width of thefield effect transistor; plurality of contacts distributed along thecontrol electrode across substantially a width of the field effecttransistor; wherein the control electrode is responsive to a signal tocontrol current flowing between the first current electrode and thesecond current electrode and to distribute the current acrosssubstantially the width of the field effect transistor.
 9. The circuitdevice of claim 8, wherein the control terminal distributes the signalto the third plurality of contacts across the width of the field effecttransistor.
 10. The circuit device of claim 9, wherein the controlterminal is adapted to couple to a switching driver circuit, the thirdplurality of contacts adapted to distribute a current density of thecurrent flowing across the width of the field effect transistor.